P. Chappel Associates, Inc.

Our client, a cutting-edge developer of custom ASICs and SoCs for emerging technologies, is seeking a Senior ASIC Design Engineer to join their growing team in San Jose. This role is ideal for engineers with stable work histories , strong customer-facing experience , and a track record of owning the full ASIC/SoC lifecycle -from initial specifications through delivery. Experience working in small, fast-moving companies is highly valued. Exposure to chiplets and datacenter applications is a strong plus. Responsibilities: Lead ASIC/SoC architecture and micro-architecture development from concept through production Collaborate closely with customers to refine requirements and ensure successful delivery Drive design reviews, documentation, verification support, and cross-functional technical alignment Provide technical leadership across security, debug, and RAS features in ARM-based systems Required Expertise: Security: Deep knowledge of SoC security architecture in ARM-based systems, including hardware Root-of-Trust, Secure Boot, ARM TrustZone, MMU/MPU, cryptographic engines, secure debug, TRNG, OTP/fuses, and tamper detection Debug: Strong experience with ARM CoreSight debug architectures-trace components, external debug interfaces, software tools; secure debug expertise highly desired RAS: Hands-on experience implementing ARM RAS features: error detection, reporting/poisoning, fault injection, and interconnect/fabric error management Qualifications: BSEE required; MSEE or advanced degree preferred Senior-level background in ASIC/SoC development with full project ownership Excellent communication skills and ability to interface directly with customers