Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at . We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation. The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues. The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces. Basic qualifications: Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor's in EE or Computer Science is required, and a Master's is preferred. 8 years' experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications. Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required experience: Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols. High level of proficiency in System Verilog and verification environments. Experience understanding software and hardware co-simulation limitations and debug methods. Experience in programming and scripting languages (like perl/python/C). Currently based locally or open to relocation. Preferred experience: Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping. Experience in modeling for emulation and prototyping, and/or non-UVM environments The base salary range is $209,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
09/24/2026
Full time
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at . We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation. The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues. The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces. Basic qualifications: Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor's in EE or Computer Science is required, and a Master's is preferred. 8 years' experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications. Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required experience: Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols. High level of proficiency in System Verilog and verification environments. Experience understanding software and hardware co-simulation limitations and debug methods. Experience in programming and scripting languages (like perl/python/C). Currently based locally or open to relocation. Preferred experience: Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping. Experience in modeling for emulation and prototyping, and/or non-UVM environments The base salary range is $209,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Qualcomm seeks a CPU Performance Analysis Engineer to optimize next generation wireless and mobile SoCs for 5G, AI, and automotive platforms. You will analyze CPU microarchitecture and system level performance, develop benchmarks and workloads, and identify bottlenecks across memory, interconnect, and power. Partner with design, architecture, and software teams to propose improvements, validate performance models, and correlate pre silicon and post silicon results. This innovative, fast paced role offers complex engineering challenges, global collaboration, and strong growth opportunities in a high impact, connectivity driven environment. Responsibilities Analyze CPU and So C performance using simulation, emulation, and silicon measurements Develop, run, and maintain performance benchmarks and workloads Identify and root cause microarchitectural and system level performance bottlenecks Collaborate with architecture and design teams to propose performance enhancements Correlate pre silicon models with post silicon measurements and refine models Generate performance reports and recommendations for future CPU and So C designs Work with software and firmware teams to optimize code for target architectures Contribute to performance tooling, automation, and data analysis pipelines Support bring up and validation of new CPU cores and So C platforms Present findings to cross functional stakeholders in a clear, data driven manner Required Skills CPU microarchitecture So C architecture Performance modeling and analysis C/C++ programming Python or similar scripting Benchmark development and profiling Linux development environment ARM or similar ISA knowledge Data analysis and visualization Simulation and emulation tools
09/23/2026
Full time
Qualcomm seeks a CPU Performance Analysis Engineer to optimize next generation wireless and mobile SoCs for 5G, AI, and automotive platforms. You will analyze CPU microarchitecture and system level performance, develop benchmarks and workloads, and identify bottlenecks across memory, interconnect, and power. Partner with design, architecture, and software teams to propose improvements, validate performance models, and correlate pre silicon and post silicon results. This innovative, fast paced role offers complex engineering challenges, global collaboration, and strong growth opportunities in a high impact, connectivity driven environment. Responsibilities Analyze CPU and So C performance using simulation, emulation, and silicon measurements Develop, run, and maintain performance benchmarks and workloads Identify and root cause microarchitectural and system level performance bottlenecks Collaborate with architecture and design teams to propose performance enhancements Correlate pre silicon models with post silicon measurements and refine models Generate performance reports and recommendations for future CPU and So C designs Work with software and firmware teams to optimize code for target architectures Contribute to performance tooling, automation, and data analysis pipelines Support bring up and validation of new CPU cores and So C platforms Present findings to cross functional stakeholders in a clear, data driven manner Required Skills CPU microarchitecture So C architecture Performance modeling and analysis C/C++ programming Python or similar scripting Benchmark development and profiling Linux development environment ARM or similar ISA knowledge Data analysis and visualization Simulation and emulation tools
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels. Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement. Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams. Drive verification planning, regression quality, coverage closure, and signoff for major SoC features. Automate verification flows using scripting, reusable infrastructure, and AI productivity tools. Mentor engineers and contribute to verification methodology and design-for-verification improvements. What You Will Learn In-depth SoC verification across compute, DDR, coherency, and Fabric NoC using modern workflows, tooling, and scripting. Integration of pre-silicon SoC verification with emulation, silicon bring-up, and platform validation strategies. How AI-driven automation reshapes modern DV workflows. Exposure to high-performance, system-level verification in advanced AI SoC designs. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
09/23/2026
Full time
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels. Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement. Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams. Drive verification planning, regression quality, coverage closure, and signoff for major SoC features. Automate verification flows using scripting, reusable infrastructure, and AI productivity tools. Mentor engineers and contribute to verification methodology and design-for-verification improvements. What You Will Learn In-depth SoC verification across compute, DDR, coherency, and Fabric NoC using modern workflows, tooling, and scripting. Integration of pre-silicon SoC verification with emulation, silicon bring-up, and platform validation strategies. How AI-driven automation reshapes modern DV workflows. Exposure to high-performance, system-level verification in advanced AI SoC designs. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels. Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement. Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams. Drive verification planning, regression quality, coverage closure, and signoff for major SoC features. Automate verification flows using scripting, reusable infrastructure, and AI productivity tools. Mentor engineers and contribute to verification methodology and design-for-verification improvements. What You Will Learn In-depth SoC verification across compute, DDR, coherency, and Fabric NoC using modern workflows, tooling, and scripting. Integration of pre-silicon SoC verification with emulation, silicon bring-up, and platform validation strategies. How AI-driven automation reshapes modern DV workflows. Exposure to high-performance, system-level verification in advanced AI SoC designs. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
09/23/2026
Full time
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels. Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, ordering, QoS, power management, error handling, and data movement. Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate closely with architecture, RTL, firmware, emulation, and system teams. Drive verification planning, regression quality, coverage closure, and signoff for major SoC features. Automate verification flows using scripting, reusable infrastructure, and AI productivity tools. Mentor engineers and contribute to verification methodology and design-for-verification improvements. What You Will Learn In-depth SoC verification across compute, DDR, coherency, and Fabric NoC using modern workflows, tooling, and scripting. Integration of pre-silicon SoC verification with emulation, silicon bring-up, and platform validation strategies. How AI-driven automation reshapes modern DV workflows. Exposure to high-performance, system-level verification in advanced AI SoC designs. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.